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2.7 GHz DDS-Based AgileRFTM Synthesizer AD9956
FEATURES
400 MSPS internal DDS clock speed 48-bit frequency tuning word 14-bit programmable phase offset Integrated 14-bit DAC Excellent dynamic performance Phase noise 135 dBc/Hz @ 1 KHz offset -80 dB SFDR @ 160 MHz (100 KHz offset IOUT) 25 Mb/s write-speed serial I/O control 200 MHz phase frequency detector inputs 655 MHz programmable input dividers for the phase frequency detector (/M, /N) {M, N = 1..16} (bypassable) Programmable RF divider (/R) {R = 1, 2, 4, 8} (bypassable) 8 phase/frequency profiles 1.8 V supply for device operation 3.3 V supply for I/O and charge pump Software controlled power-down 48-lead LFCSP package Automatic linear frequency sweeping capability (in DDS) Programmable charge pump current (up to 4 mA) Phase modulation capability Multichip synchronization Dual-mode PLL lock detect 655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
DAC_RSET
DELTA FREQUENCY TUNING WORD FREQUENCY ACCUMULATOR DELTA FREQUENCY RAMP RATE 16 FTW 48
48
PHASE OFFSET 19
DDS CORE PHASE TO AMPLITUDE CONVERSION 14 IOUT DAC IOUT
PHASE ACCUMULATOR PHASE OFFSET WORD 14
24 PLL_LOCK/SYNC_IN I/O_UPDATE
SYSCLK
SYSCLK I/O_RESET LOCK DETECT CHARGE PUMP SCALER 3 /N CHARGE PUMP
TIMING AND CONTROL LOGIC OSCILLATOR
SYNC_OUT
SYNC_CLK RF-DIVIDER /R
/4
SYSCLK
/M
REFCLK REFCLK CML CLOCK DRIVER 3 FROM PLLOSC DRV DRV DRV_RSET PS<2:0> RESET I/O PORT PLLREF/ PLLREF BUFFER
04806-0-001
BUFFER
CP_OUT
PLLOSC/ PLLOSC
CP_RSET
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9956 TABLE OF CONTENTS
Product Overview............................................................................. 3 Specifications..................................................................................... 4 Loop Measurement Conditions.................................................. 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Typical Application Circuits.......................................................... 16 Application Circuit Explanations............................................. 17 General Description ....................................................................... 18 DDS Core..................................................................................... 18 PLL Circuitry .............................................................................. 18 CML Driver................................................................................. 19 Modes of Operation ....................................................................... 20 DDS Modes of Operation ......................................................... 20 Synchronization Modes for Multiple Devices.............................. 20 Serial Port Operation ..................................................................... 22 Instruction Byte .......................................................................... 23 Serial Interface Port Pin Description....................................... 23 MSB/LSB Transfers .................................................................... 23 Register Map and Description ...................................................... 24 Control Function Register Descriptions ................................. 27 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
7/04--Revision: Initial Version
Rev. 0 | Page 2 of 32
AD9956 PRODUCT OVERVIEW
The AD9956 is Analog Devices' newest AgileRF synthesizer. The device is comprised of DDS and PLL circuitry. The DDS features a 14-bit DAC operating at up to 400 MSPS and a 48-bit frequency tuning word (FTW). The PLL circuitry includes a phase frequency detector with scaleable 200 MHz inputs (divider inputs operate up to 655 MHz) and digital control over the charge pump current. The device also includes a 655 MHz CML-mode PECL-compliant driver with programmable slew rates. The AD9956 uses advanced DDS technology, an internal high speed, high performance DAC, and an advanced phase frequency detector/charge pump combination, which, when used with an external VCO, enables the synthesis of digitally programmable, frequency-agile analog output sinusoidal waveforms up to 2.7 GHz. The AD9956 is designed to provide fast frequency hopping and fine tuning resolution (48-bit frequency tuning word). Information is loaded into the AD9956 via a serial I/O port that has a device write-speed of 25 Mb/s. The AD9956 DDS block also supports a user-defined linear sweep mode of operation. The AD9956 is specified to operate over the extended automotive range of -40C to +125C.
Rev. 0 | Page 3 of 32
AD9956 SPECIFICATIONS
AVDD = DVDD = 1.8 V 5%; DVDD_I/O = CP_VDD = 3.3 V 5% (@ TA = 25C) DAC_RSET = 3.92 k, CP_RSET = 3.09 k, DRV_RSET = 4.02 k, unless otherwise noted. Table 1.
Parameter RF DIVIDER (REFCLK ) INPUT SECTION (/R) RF Divider Input Range Input Capacitance (DC) Input Impedance (DC) Input Duty Cycle Input Power/Sensitivity Input Voltage Level PHASE FREQUENCY DETECTOR/CHARGE PUMP PLLREF Input Input Frequency2 /M Set to Divide by at Least 4 /M Bypassed Input Voltage Levels Input Capacitance Input Resistance PLLOSC Input Input Frequency /N Set to Divide by at Least 4 /N Bypassed Input Voltage Levels Input Capacitance Input Resistance Charge Pump Source/Sink Maximum Current Charge Pump Source/Sink Accuracy Charge Pump Source/Sink Matching Charge Pump Output Compliance Range3 PLL_LOCK Drive Strength PHASE FREQUENCY DETECTOR NOISE FLOOR @ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 100 MHz PFD Frequency @ 200 MHz PFD Frequency CML OUTPUT DRIVER (DRV) Differential Output Voltage Swing4 Maximum Toggle Rate Common-Mode Output Voltage Output Duty Cycle Output Current Continuous5 Rising Edge Surge Falling Edge Surge Output Rise Time Min 1 3 1500 50 Typ Max 2700 Unit MHz pF % dBm mV p-p Test Conditions/Comments DDS SYSCLK not to exceed 400 MSPS
42 -10 350
58 +4 1000
Single-ended, into a 50 load1
200
450 1500
655 200 600 10
MHz MHz mV p-p pF
200
450 1500
655 200 600 10 4 +5 +5 CP_VDD - 0.5
-15 -5 0.5 2 149 133 116 113 720 655 42 1.75 50 7.2 20.9 13.5 250
MHz MHz mV p-p pF mA % % V mA dBc/Hz dBc/Hz dBc/Hz dBc/Hz mV MHz V % mA mA mA ps 50 load to supply, both lines
58
100 terminated, 5 pF load
Rev. 0 | Page 4 of 32
AD9956
Parameter LOGIC INPUTS (SDI/O, I/O_RESET, RESET, I/O_UPDATE, PS0 to PS2, SYNC_IN) VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL Input Current CIN, Maximum Input Capacitance LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)6 VOH, Output High Voltage VOH, Output Low Voltage IOH IOL POWER CONSUMPTION Total Power Consumed, All Functions On IAVDD IDVDD IDVDD_I/O ICP_VDD Power-Down Mode WAKE-UP TIME (from Power-Down Mode) Digital Power-Down (CFR1<7>) DAC Power-Down (CFR2<39>) RF Divider Power-Down (CFR2<23>) Clock Driver Power-Down (CFR2<20>) Charge Pump Full Power-Down (CFR2<4>) Charge Pump Quick Power-Down (CFR2<3>) DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Output Capacitance Voltage Compliance Range Wideband SFDR (DC to Nyquist) 10 MHz Analog Out 40 MHz Analog Out 80 MHz Analog Out 120 MHz Analog Out 160 MHz Analog Out Narrowband SFDR 10 MHz Analog Out (1 MHz) 10 MHz Analog Out (250 kHz) 10 MHz Analog Out (50 kHz) 40 MHz Analog Out (1 MHz) 40 MHz Analog Out (250 kHz) 40 MHz Analog Out (50 kHz) 80 MHz Analog Out (1 MHz) 80 MHz Analog Out (250 kHz) 80 MHz Analog Out (50 kHz) 120 MHz Analog Out (1 MHz) 120 MHz Analog Out (250 kHz) 120 MHz Analog Out (50 kHz) Min Typ Max Unit Test Conditions/Comments
2.0 1 3 2.7 0.4 100 100 400 85 45 20 15 80 12 7 400 6 10 150 14 10 -10 5 AVDD - 0.50 -64 -62 -60 -55 -55 -89 -91 -93 -87 -89 -91 -85 -87 -89 -83 -85 -87 AVDD + 0.50 0.8 5
V V A pF V V A A mW mA mA mA mA mW ns s ns s s ns Bits mA % FS A pF V dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
15 +10 0.6
Rev. 0 | Page 5 of 32
AD9956
Parameter 160 MHz Analog Out (1 MHz) 160 MHz Analog Out (250 kHz) 160 MHz Analog Out (50 kHz) DAC Residual Phase Noise 19.7 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 51.84 MHz FOUT @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 105.3 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset 155.52 MHz Analog Out @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CRYSTAL OSCILLATOR (ON PLLREF INPUT) Operating Range Residual Phase Noise (@ 25 MHz) @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset DIGITAL TIMING SPECIFICATIONS CS to SCLK Setup Time TPRE Period of SCLK (Write Speed) TSCLKW Period of SCLK (Read Speed) TSCLKR Serial Data Setup Time TDSU Serial Data Hold Time TDHLD TDV Data Valid Time TDV I/O Update to SYNC_CLK Setup Time TUD PS<2:0> to SYNC_CLK Setup Time TPS Min Typ -81 -83 -85 Max Unit dBc dBc dBc Test Conditions/Comments
125 135 143 152 158 163 119 125 132 142 150 155 105 115 122 131 139 142 105 110 119 127 135 142 20 25 95 120 137 156 164 170 6 40 400 6.5 0 40 7 7 30
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ns ns ns ns ns ns ns ns
Rev. 0 | Page 6 of 32
AD9956
Parameter Latencies/Pipeline Delays7 I/O Update to DAC Frequency Change I/O Update to DAC Phase Change PS<2:0> to DAC Frequency Change PS<2:0> to DAC Phase Change I/O Update to CP_OUT Scaler Change I/O Update to Frequency Accumulator Step Size Change I/O Update to Frequency Accumulator Ramp Rate Change RF DIVIDER/CML DRIVER EQUIVALENT INTRINSIC TIME JITTER FIN = 414.72 MHz, FOUT = 51.84 MHz BW = 12 kHz -> 400 kHz FIN = 1244.16 MHz, FOUT = 155.52 MHz BW = 12 kHz -> 1.3 MHz FIN = 2488.32 MHz, FOUT = 622.08 MHz BW = 12 kHz -> 5 MHz RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE FIN = 157.6 MHz, FOUT = 19.7 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz > 1 MHz FIN = 1240 MHz, FOUT = 155 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz FIN = 2488MHz, FOUT = 622 MHz @ 10 Hz @ 100 Hz @ 1 kHz @ 10 kHz @ 100 kHz @ 1 MHz >3 MHz TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK 12 kHz to 5 MHz Bandwidth Min Typ 33 33 29 29 4 4 4 Max Unit SYSCLK Cycles SYSCLK Cycles SYSCLK Cycles SYSCLK Cycles SYSCLK Cycles SYSCLK Cycles SYSCLK Cycles Test Conditions/Comments
136 101 108
fS rms fS rms fS rms
OC1, RF Divider R = 8 OC3, RF Divider R = 8 OC12, RF Divider R = 4 RF Divider R = 8
-115 -126 -134 -143 -150 -151 -111 -122 -129 -138 -146 -150 -153 -97 -110 -120 -126 -136 -141 -144
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz RF Divider R = 8 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz RF Divider R = 4 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz See the Loop Measurement Conditions section
0.7
ps rms
Rev. 0 | Page 7 of 32
AD9956
Parameter TOTAL SYSTEM JITTER AND PHASE NOISE FOR 105.33 MHz ADC CLOCK GENERATION CIRCUIT Converter Limiting Jitter Resultant SNR Phase Noise of Fundamental @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset Min Typ Max Unit Test Conditions/Comments See the Loop Measurement Conditions section
0.53 67 -75 -87 -93 -105 -145 -152
ps rms dB dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
1 2
The input impedance of the REFCLK input is 1500 . However, in order to provide matching on the clock line, an external 50 load is used. Driving the PLLREF input buffer, the crystal oscillator section of this input stage performs up to only 30 MHz. 3 The charge pump output compliance range is functionally 0.2 V to (CP_VDD - 0.2 V). The value listed here is the compliance range for 5% matching. 4 Measured as peak-to-peak from DRV to DRV. 5 For a 4.02 k resistor from DRV_RSET to GND. 6 Assumes a 1 mA load. 7 I/O_UPDATE/PS<2:0> are detected by the AD9956 synchronous to the rising edge of SYNC_CLK. Each latency measurement is from the first SYNC_CLK rising edge after the I/O_UPDATE/PS<2:0> state change.
Rev. 0 | Page 8 of 32
AD9956
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
VCO = Sirenza 190-640T Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 60 Phase Margin C1 = 170 nF, R1 = 14.4 , C2 = 5.11 F, R2 = 89.3 , C3 Omitted CP_OUT = 4 mA (Scaler = x8) /R = 2, /M = 1, /N = 1
INPUT R1 C1 C2 C3
04806-0-033
105 MHz Converter Clock
VCO = Sirenza 190-845T Reference = Wenzel 500-10116 (30.3 MHz) Loop Filter = 10 kHz BW, 45 Phase Margin C1 = 117 nF, R1 = 28 , C2 = 1.6 F, R2 = 57.1 , C3 = 53.4 nF CP_OUT = 4 mA (Scaler = x8) /R = 8, /M = 1, /N = 1
R2
OUTPUT
Figure 2. Generic Loop Filter
Rev. 0 | Page 9 of 32
AD9956 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/0) Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Thermal Resistance (JA) Rating 2V 2V 3.6 V 3.6 V -0.5 V to DVDD_I/O + 0.5 V -65C to +150C -40C to +125C 300C 150C 26C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 10 of 32
AD9956 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD DAC_RSET DRV_RSET CP_RSET AVDD AGND PLLOSC PLLOSC PLLREF PLLREF AVDD AGND 48 47 46 45 44 43 42 41 40 39 38 37
AGND AVDD
1 2
PIN 1 INDICATOR
AGND 3 AVDD 4 IOUT 5 IOUT 6 AVDD 7 AGND 8 I/O_RESET 9 RESET 10 DVDD 11 DGND 12 NC = NO CONNECT
36 35 34 33 32 31 30 29 28 27 26 25
CP_OUT CP_VDD AGND DRV DRV AVDD AGND REFCLK REFCLK AVDD AGND DVDD
AD9956
TOP VIEW (Not to Scale)
SDO SDI/O SCLK CS DVDD_I/O SYNC_OUT PLL_LOCK/SYNC_IN I/O_UPDATE PS0 PS1 PS2 DGND
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. 48-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. For the device to function properly, the paddle MUST be attached to analog ground.
Rev. 0 | Page 11 of 32
04806-0-008
AD9956
Table 3. 48-Lead LFCSP Pin Function Description
Pin No. 1, 3, 8, 26, 30, 34, 37, 43, 49 2, 4, 7, 27, 31, 38, 44, 48 5 6 9 Mnemonic AGND AVDD IOUT IOUT I/O_RESET Description Analog Ground. Analog Core Supply (1.8 V). DAC Analog Output. DAC Analog Complementary Output. Resets the serial port when synchronization is lost in communications but does not reset the device itself (ACTIVE HIGH). When not being used, this pin should be forced low, because it floats to the threshold value. Master RESET. Clears all accumulators and returns all registers to their default values (ACTIVE HIGH). Digital Core Supply (1.8 V). Digital Ground. Serial Data Output. Used only when device is programmed for 3-wire serial data mode. Serial Data I/O. When the part is programmed for 3-wire serial data mode, this is input only; in 2-wire mode, it serves as both the input and output. Serial Data Clock. Provides the clock signal for the serial data port. Active Low Signal That Enables Shared Serial Busses. When brought high, the serial port ignores the serial data clocks. Digital Interface Supply (3.3 V). Synchronization Clock Output. Bidirectional Dual Function Pin. Depending on device programming, it is either the DDS' synchronization input (allows alignment of multiple subclocks) or the PLL lock detect output signal. This input pin, when set high, transfers the data from the I/O buffers to the internal registers on the rising edge of the internal SYNC_CLK, which can be observed on SYNC_OUT. Profile Select Pins. Specify one of eight frequency tuning word/phase offset word profiles. In linear sweep mode, PS0 determines the state of the sweep. In linear sweep no dwell mode, PS0 is a trigger that initiates the sweep. PS1 and PS2 have no function during linear sweep mode or linear sweep no dwell mode. RF Divider and DDS REFCLK Complementary Input. RF Divider and DDS REFCLK Input. CML Driver Complementary Output. CML Driver Output. Charge Pump Supply Pin (3.3 V). To minimize noise on the charge pump, isolate this supply from DVDD_I/O. Charge Pump Output. Phase Frequency Detector Reference Input. Phase Frequency Detector Reference Complementary Input. Phase Frequency Detector Oscillator (Feedback) Complementary Input. Phase Frequency Detector Oscillator (Feedback) Input. Charge Pump Current Set (Program Charge Pump Current with a Resistor to AGND). CML Driver Output Current Set (Program CML Output Current with a Resistor to AGND). DAC Output Current Set (Program DAC Output Current with a Resistor to AGND).
10 11, 25 12, 24 13 14 15 16 17 18 19 20 21 to 23
RESET DVDD DGND SDO SDI/O SCLK CS DVDD_I/O SYNC_OUT PLL_LOCK/SYNC_IN I/O_UPDATE PS0 to PS2
28 29 32 33 35 36 39 40 41 42 45 46 47
REFCLK REFCLK DRV DRV CP_VDD CP_OUT PLLREF PLLREF PLLOSC PLLOSC CP_RSET DRV_RSET DAC_RSET
Note that the exposed paddle on this package is an electrical connection (Pin 49) as well as a thermal enhancement. In order for the device to function properly, the paddle MUST be attached to analog ground.
Rev. 0 | Page 12 of 32
AD9956 TYPICAL PERFORMANCE CHARACTERISTICS
REF LVL 0dBm 0 -10 -20 -30 -40 1 AP -50 -60 -70 -80
04806-0-015
DELTA 1 [T1] -84.82dB -404.80961924kHz
1
RBW 500Hz VBW 500Hz 20s SWT
RF ATT 20dB UNIT dB 0
A
REF LVL 0dBm
1
DELTA 1 [T1] -67.45dB 74.50901804MHz
RBW 10kHz VBW 10kHz 4.3s SWT
RF ATT 20dB UNIT dB
A
-10 -20 -30 -40 1 AP -50 -60 -70 -80
1 1
-90 -100
-90 -100 START 0Hz 16.9MHz/ STOP 169MHz
CENTER 10.1MHz
100kHz/
SPAN 1MHz
Figure 4. AD9956 DAC Performance: 400 MSPS Clock, 10 MHz FOUT, 1 MHz Span
REF LVL 0dBm 0 -10 -20 -30 -40 1 AP -50 -60 -70 -80 -90 -100 CENTER 40.1MHz 100kHz/ SPAN 1MHz
1
04806-0-016
Figure 7. AD9956 DAC Performance: 400 MSPS Clock, 10 MHz FOUT, 200 MHz Span
REF LVL 0dBm 0
A
DELTA 1 [T1] -78.67dB -100.20040080kHz
1
RBW 500Hz VBW 500Hz 20s SWT
RF ATT 20dB UNIT dB -10 -20 -30 -40
DELTA 1 [T1] -62.65dB 100.20040080MHz
1
RBW 10kHz VBW 10kHz 5s SWT
RF ATT 20dB UNIT dB
A
1 AP -50 -60
1
-70 -80 -90 -100 START 0Hz 20MHz/ STOP 200MHz
04806-0-019
Figure 5. AD9956 DAC Performance: 400 MSPS Clock, 40 MHz FOUT, 1 MHz Span
REF LVL 0dBm 0 -10 -20 -30 -40 1 AP -50 -60 -70 -80
04806-0-017
Figure 8. AD9956 DAC Performance: 400 MSPS Clock, 40 MHz FOUT, 200 MHz Span
REF LVL 0dBm 0
A
DELTA 1 [T1] -57.74dB -400.80160321kHz
1
RBW 500Hz VBW 500Hz 20s SWT
RF ATT 20dB UNIT dB -10 -20 -30 -40
DELTA 1 [T1] -48.78dB -400.80160321kHz
1
RBW 10kHz VBW 10kHz 5s SWT
RF ATT 20dB UNIT dB
A
1 AP -50
1
1
-60 -70 -80 -90 -100 START 0Hz 20MHz/ STOP 200MHz
04806-0-020
-90 -100 CENTER 100.1MHz 100kHz/ SPAN 1MHz
Figure 6. AD9956 DAC Performance: 400 MSPS Clock, 100 MHz FOUT, 1 MHz Span
Rev. 0 | Page 13 of 32
Figure 9. AD9956 DAC Performance: 400 MSPS Clock, 100 MHz FOUT, 200 MHz Span
04806-0-018
AD9956
REF LVL 0dBm 0
1 A
DELTA 1 [T1] -78.13dB -100.20040080kHz
RBW 500kHz VBW 500kHz 20s SWT
RF ATT 20dB UNIT dB 0 -10 -20 -30 -40 1 AP REF LVL 0dBm
DELTA 1 [T1] -56.33dB -80.96192385MHz
RBW 10kHz VBW 10kHz 5s SWT
RF ATT 20dB UNIT
1
dB
A
-10 -20 -30 -40 -50 -60 -70 -80
04806-0-021
1 AP -50 -60 -70 -80 -90 -100 START 0Hz 20MHz/ STOP 200MHz
04806-0-022
1
1
-90 -100 CENTER 159.5MHz 100kHz/ SPAN 1MHz
Figure 10. AD9956 DAC Performance: 400 MSPS Clock, 160 MHz FOUT, 1 MHz Span
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
Figure 13. AD9956 DAC Performance: 400 MSPS Clock, 160 MHz FOUT, 200 MHz Span
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
L(f) (dBc/Hz)
04806-0-023
L(f) (dBc/Hz)
100
1k 10k FREQUENCY (Hz)
100k
1M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 11. AD9956 DDS/DAC Residual Phase Noise 400 MHz Clock, 10 MHz Output
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
Figure 14. AD9956 DDS/DAC Residual Phase Noise 400 MHz Clock, 103 MHz Output
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
L(f) (dBc/Hz)
04806-0-024
L(f) (dBc/Hz)
100
1k 10k FREQUENCY (Hz)
100k
1M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 12. AD9956 DDS/DAC Residual Phase Noise 400 MHz Clock, 40 MHz Output
Figure 15. AD9956 DDS/DAC Residual Phase Noise 400 MHz Clock, 159 MHz Output
Rev. 0 | Page 14 of 32
04806-0-026
04806-0-025
AD9956
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
L(f) (dBc/Hz)
04806-0-027
L(f) (dBc/Hz)
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100M
Figure 16. RF Divider and CML Driver Residual Phase Noise (840 MHz In, 105 MHz Out)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10
Figure 19. RF Divider and CML Driver Residual Phase Noise (2488 MHz In, 622 MHz Out)
L(f) (dBc/Hz)
04806-0-028
L(f) (dBc/Hz)
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 17. RF Divider and CML Driver Residual Phase Noise (1240 MHz In, 155 MHz Out)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 10
Figure 20. Total System Phase Noise for 105 MHz Converter Clock
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 10
L(f) (dBc/Hz)
L(f) (dBc/Hz)
04806-0-029
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 18. RF Divider and CML Driver Residual Phase Noise (1680 MHz In, 210 MHz Out)
Figure 21. Total System Phase Noise for 622 MHz OC-12 Clock
Rev. 0 | Page 15 of 32
04806-0-032
04806-0-031
04806-0-030
AD9956 TYPICAL APPLICATION CIRCUITS
25MHz CRYSTAL PHASE FREQUENCY DETECTOR/CHARGE PUMP /M PLLREF CP_OUT /N PLLOSC LPF 400MHz VCO
CML DRIVER /R CLOCK1
DDS
DAC LPF
CLOCK1
Figure 22. Dual-Clock Configuration
PLLREF CP_OUT PLLOSC VCO LPF
LPF
AD9956
Figure 23. Fractional-Divider Loop
CML DRIVER
DDS
DAC BPF
8-LEVEL FSK (FC = 100MHz)
/R
AD9956
25MHz CRYSTAL /N PLLREF CP_OUT PLLOSC LPF VCO 2.5GHz TONE
04806-0-011
DAC
DDS
/R
BPF
Figure 24. LO and Baseband Modulation Generation
Rev. 0 | Page 16 of 32
04806-0-012
04806-0-010
AD9956
AD9956
EXTERNAL REFERENCE PHASE FREQUENCY DETECTOR /M /N REF CHARGE PUMP
622MHz VCO LPF CML DRIVER CLOCK1
OSC
/R
DDS
DAC
CLOCK2
Figure 25. Optical Networking Clock
PHASE FREQUENCY DETECTOR DDS DAC LPF /N PLLOSC CHARGE PUMP VCO LPF
04806-0-014
PLLREF 650MHz
Figure 26. Direct Upconversion
APPLICATION CIRCUIT EXPLANATIONS
Dual-Clock Configuration In this loop, M = 1, N = 16, and R = 4. The DDS tuning word is also equal to 1/4 so that the frequency of CLOCK 1' equals the frequency of CLOCK 1. Phase adjustments in the DDS provide a 14-bit programmable rising edge skew capability of CLOCK 1' with respect to CLOCK 1 (see Figure 22). Fractional-Divider Loop This loop offers the precise frequency division (48-bit) of the DDS in the feedback path as well as the frequency sweeping capability of the DDS. Programming the DDS to sweep from 24 MHz to 25 MHz sweeps the output of the VCO from 2.7 GHz to 2.6 GHz. The reference in this case is a simple crystal (see Figure 23).
LO and Baseband Modulation Generation Using the AD9956's PLL section to generate an LO and the DDS portion to generate a modulated baseband, this circuit uses an external mixer to perform some simple modulation at RF frequencies (see Figure 24). Optical Networking Clock This is the AD9956 configured as an optical networking clock. The loop can be used to generate a 622 MHz clock for OC12. The DDS can be programmed to output 8 kHz to serve as a base reference for other circuits in the subsystem (see Figure 25). Direct Upconversion The AD9956 is configured to use the DDS as a precision reference to the PLL loop. Since the VCO is < 655 MHz, it can be fed straight into the phase frequency detector feedback input (with the divider enabled), as seen in Figure 26.
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AD9956
AD9956 GENERAL DESCRIPTION
DDS CORE
The DDS can create digital phase relationships by clocking a 48-bit accumulator. The incremental value loaded into the accumulator, known as the frequency tuning word, controls the overflow rate of the accumulator. Similar to a sine wave completing a 2 radian revolution, the overflow of the accumulator is cyclical in nature and generates a base frequency according to the following equation.
fo =
FTW x ( f s ) 248
{0 FTW 247 }
The instantaneous phase of the sine wave is, therefore, the output of the phase accumulator block. This signal can be phaseoffset by programming an additive digital phase added to each and every phase sample coming out of the accumulator. These instantaneous phase values are then piped through a phase-to-amplitude conversion (sometimes called an angleto-amplitude conversion or AAC) block. This algorithm follows a COS(x) relationship where x is the phase coming out of the phase offset block, normalized to 2. Finally, the amplitude words are piped to a 14-bit DAC. Because the DAC is a sampled data system, the output is a reconstructed sine wave that needs to be filtered to take high frequency images out of the spectrum. The DAC is a current-steering DAC that is AVDD referenced. To get a measurable voltage output, the DAC outputs must terminate through a load resistor to AVDD, typically 50 . At positive full scale, IOUT sinks no current and the voltage drop across the load resistor is zero. However, the IOUT output sinks the DAC's programmed fullscale output current, causing the maximum output voltage to drop across the load resistor. At negative full-scale, the situation is reversed and IOUT sinks the full-scale current (and generates the maximum drop across the load resistor). At the same time, IOUT sinks no current (and generates no voltage drop). At midscale, the outputs sink equal amounts of current, generating equal voltage drops.
The RF divider accepts differential or single-ended signals up to 2.7 GHz. The RF divider also supplies the SYSCLK input to the DDS. Because the DDS operates up to only 400 MSPS, device function requires that for any RF input signal > 400 MHz, the RF divider be engaged. The RF divider can be programmed to take values of 1, 2, 4, or 8. The ratio for the divider is programmed in the control register. The output of the divider can be routed to the input of the on-chip CML driver. For lower frequency input signals, it is possible to use the divider to divide the input signal to the CML driver and use the undivided input of the divider as the SYSCLK input to the DDS, or vice versa. In all cases, the clock to the DDS should not exceed 400 MSPS. The on-chip phase frequency detector has two differential inputs, PLLREF (the reference input) and PLLOSC (the feedback or oscillator input). These differential inputs can be driven by single-ended signals; however, when doing so, tie the unused input through a 100 pF capacitor to the analog supply (AVDD). The maximum speed of the phase frequency detector inputs is 200 MHz. Each of the inputs has a buffer and a divider (/M on PLLREF and /N on PLLOSC) that operates at up to 655 MHz. If the signal exceeds 200 MHz, however, the divider must be used. The dividers are programmed through the control registers and take any integer value between 1 and 16. The PLLREF input also has the option of engaging an in-line oscillator circuit. Engaging this circuit means that the PLLREF input can be driven with a crystal in the of 20 MHz PLLREF 30 MHz range. The charge pump outputs a current in response to an error signal generated in the phase frequency detector. The output current is programmed through by placing a resistor (CP_RSET) from the CP_RSET pin to ground. The value is dictated by the following equation:
CP_OUT =
1.55 CP_RSET
PLL CIRCUITRY
The AD9956 includes an RF divider (divide-by-R), a phase frequency detector, and a programmable output current charge pump. Incorporating these blocks together, users can generate many useful circuits for frequency synthesis. A few simple examples are shown in the Typical Application Circuits.
This sets the charge pump's reference output current. Also, a programmable scaler multiplies this base value by any integer from 1 to 8, programmable through the CP current scale bits in the Control Function Register 2, CFR2<2:0>.
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AD9956
CML DRIVER
For clocking applications, an on-chip current mode logic (CML) driver is included. This CML driver generates very low jitter clock edges. The outputs of the CML driver are current outputs and drives PECL levels when terminated into a 100 load. The base output current of the driver is programmed by attaching a resistor from the DRV_RSET pin to ground (nominally 4.02 k for a continuous current of 7.2 mA). An optional on-chip current programming resistor is enabled by setting a bit in the control register. The rising edge and falling edge slew rates are independently programmable to help control overshoot and ringing through the application of surge current during rising edge transitions and falling edge transitions (see Figure 27). There is a default surge current of 7.6 mA on the rising edge and 4.05 mA on the falling edge. Bits in the control register enable additional rising edge and falling edge surge current, as well disable the default surge current (see the Control Function Register Descriptions section for details). The CML driver can be driven by the
* * *
RISING EDGE SURGE
I(t)
CONTINUOUS
CONTINUOUS
FALLING EDGE SURGE
t
~250ps ~250ps
RF divider input RF divider output PLLOSC input
Figure 27. Rising Edge and Falling Edge Surge Current Output of the CML Clock Driver, as Opposed to the Steady State Continuous Current
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AD9956 MODES OF OPERATION
DDS MODES OF OPERATION
Single-Tone Mode
This is the default mode of operation for the DDS core. The phase accumulator runs at a fixed frequency, as per the active profile's tuning word. Likewise, any phase offset applied to the signal is a static value, which comes from the phase offset word of the active profile. The device has eight different phase/frequency profiles, each with its own 48-bit frequency tuning word and 14-bit phase offset word. Profiles are selected by applying their digital value on the profile-select pins (PS2, PS1, and PS0). It is impossible to use the phase offset of one profile and the frequency tuning word of another. If a sweep is interrupted and the state of the PS0 pin is changed during the midst of a sweep, the part begins sweeping in the new direction at the rate dictated by the relevant delta frequency tuning word and sweep ramp rate word. For example, if the part is programmed to sweep from 100 MHz to 140 MHz and to take 1 kHz steps every 1000 sync clock cycles (rising and falling sweep words are the same), it would take four seconds to complete a sweep. If the PS0 has been low for a very long time (more than four seconds), changing the PS0 pin to high starts a sweep up to 140 MHz. If after two seconds (not enough time for a full sweep in this example) the PS0 pin is brought low again, the part begins sweeping down from the current value, roughly 120 MHz.
Linear Sweep Mode
This mode is entered by setting the linear sweep enable bit in the control register (CFR1<17> = 1) but leaving the linear sweep no dwell bit clear (CFR1<16> = 0). When the part is in linear sweep mode, the frequency accumulator ramps the output frequency of the device from a programmed lower frequency to a programmed upper frequency or from the upper frequency to the lower frequency. The lower frequency is set by the frequency tuning word stored in Profile 0, and the upper frequency is set by the frequency tuning word stored in Profile 1. The combinational logic within the frequency accumulator requires that the value stored at FTW0 must always be less than the value stored in FTW. The direction of the sweep (sweep up to FTW1, sweep down to FTW0) is controlled by the PS0 pin. A high state on this pin tells the part to sweep up to FTW1. A low state on this pin tells the part to sweep down to FTW0. The frequency accumulator requires four values, which are stored in the register map. First, it requires an incremental frequency value that tells the frequency accumulator how big of a frequency step to take each time it takes a step when ramping up. This value is stored in the rising delta frequency tuning word (RDFTW). The second value required is the rate at which the frequency accumulator should increment, that is, how often it should take a step. This value is stored in the rising sweep ramp rate word (RSRR). The RSRR value specifies the number of SYNC_CLK cycles the frequency accumulator should count between steps. The third and fourth values are the falling ramp equivalents, the falling delta frequency tuning word (FDFTW) and the falling sweep ramp rate (FSRR). When operating in the linear sweep default mode, combinational logic ensures that the part never ramps up past FTW1, even if the next RDFTW increments the frequency past FTW1. Once it reaches FTW1, as long as the PS0 pin stays high, the frequency remains at FTW1. Likewise, the internal logic ensures that the part never ramps down past FTW0, even if the next RDFTW increments the frequency past FTW0. During a sweep down (PS0 = 0), once the part reaches FTW0, as long as the PS0 pin stays low, the frequency remains at FTW0.
Linear Sweep No Dwell Mode
This mode is entered by setting the linear sweep enable bit and the linear sweep no dwell bit in the control register (CFR<17:16> =1). When the part is in linear sweep no dwell mode, the frequency accumulator ramps the output frequency of the device from a programmed lower frequency to a programmed upper frequency. Upon reaching the upper frequency, the accumulator returns to the lower frequency directly, without ramping back down. Unlike the default mode of the linear sweep, this mode uses only the rising delta frequency tuning word (RDFTW) and the rising sweep ramp rate (RSRR). The operation is still controlled by the PS0 pin. In this mode, however, it acts as a trigger for the sweep, not a direction bit. Once a PS0 low-to-high transition is detected, the part completes the entire sweep, regardless of whether or not the PS0 pin is changed back to low during the sweep. After the sweep is completed, another sweep may be initiated by applying another rising edge on the PS0 pin. This means that the PS0 pin needs to be brought low prior to the next sweep.
SYNCHRONIZATION MODES FOR MULTIPLE DEVICES
In a DDS system, the SYNC_CLK is derived internally off the master system clock, SYSCLK, with a /4 divider. Because the divider does not power up to a known state, it is possible for multiple devices in a system to have staggered clock-phase relationships. This is because each device could potentially generate the SYNC_CLK rising edge from any one of four rising edges of SYSCLK. This ambiguity can be resolved by employing digital synchronization logic to control the phase relationships of the derived clocks among different devices in the system. It is important to note that the synchronization functions included on the AD9956 control only the timing relationships among different digital clocks. They do not compensate for the analog timing skew on the system clock due to mismatched phase relationships on the input clock, REFCLK. Figure 28 illustrates this concept.
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AD9956
Automatic Synchronization
In automatic synchronization mode, the device is placed into slave mode and automatically aligns the internal SYNC_CLK to a master SYNC_CLK signal, supplied on the SYNC_IN input. When this bit is enabled, the PLL_LOCK is not available as an output, however, an out-of-lock condition can be detected by reading Control Function Register 1 and checking the status of the PLL_LOCK_ERROR bit, CFR1<24>. The automatic synchronization function is enabled by setting the Control Function Register 1 automatic synchronization bit, CFR1<3>. To employ this function at higher clock rates (SYNC_CLK > 62.5 MHz and SYSCLK > 250 MHz), the high speed sync enable bit (CFR1<0>) should be set as well.
Manual Synchronization, Software Controlled
In this mode, the user controls the timing relationship between SYNC_CLK and SYSCLK through software programming. When the software manual synchronization bit (CFR1<2>) is set high, the SYNC_CLK is advanced by one SYSCLK cycle. Once this operation is complete, the bit is cleared. The user can set this bit repeatedly to advance the SYNC_CLK rising edge multiple times. Because the operation does not use the PLL_LOCK/ SYNC_IN pin as a SYNC_IN input, the PLL_LOCK signal can be monitored on the PLL_LOCK pin during this operation.
Manual Synchronization, Hardware Controlled
In this mode, the user controls the timing relationship of the SYNC_CLK with respect to SYSCLK. When hardware manual synchronization is enabled, the PLL_LOCK/ SYNC_IN pin becomes a digital input. For each and every rising edge detected on the SYNC_IN input, the device advances the SYNC_IN rising edge by one SYSCLK period. When this bit is enabled, the PLL_LOCK is not available as an output. However, an out-oflock condition can be detected by reading Control Function Register 1 and checking the status of the PLL Lock Error bit, CFR1<24>. This synchronization function is enabled by setting the hardware manual synchronization enable bit, CFR1<1>.
SYNCHRONIZATION FUNCTIONS CAN ALIGN DIGITAL CLOCK RELATIONSHIPS, THEY CANNOT DESKEW THE EDGES OF CLOCKS
SYSCLK DUT 1 SYNC CLK DUT1 SYSCLK DUT 2 SYNC CLK DUT2 WITHOUT SYNC_CLK ALIGNED SYNC CLK DUT2 WITH SYNC_CLK ALIGNED
0
1
2
3
0
3
0
1
2
3
Figure 28. Synchronization Functions: Capabilities and Limitations
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AD9956 SERIAL PORT OPERATION
An AD9956 serial data-port communication cycle has two phases. Phase 1 is the instruction cycle, which is the writing of an instruction byte to the AD9956, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9956 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9956. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9956 and the system controller. The number of bytes transferred during Phase 2 of the communication cycle is a function of the register being accessed. For example, when accessing Control Function Register 2, which is four bytes wide, Phase 2 requires that four bytes be transferred. If accessing a frequency tuning word, which is six bytes wide, Phase 2 requires that six bytes be transferred. After transferring all data bytes per the instruction, the communication cycle is completed. At the completion of any communication cycle, the AD9956 serial port controller expects the next eight rising SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9956 is registered on the rising edge of SCLK. All data is driven out of the AD9956 on the falling edge of SCLK. Figure 29 through Figure 32 are useful in understanding the general operation of the AD9956 serial port.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK SDI/O I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 29. Serial Port Write Timing--Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK I7 I6 I5 I4 I3 I2 I1 I0 DO 7 DON'T CARE DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
SDO
Figure 30. 3-Wire Serial Port Read Timing--Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK SDI/O I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 31. Serial Port Write Timing--Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK SDI/O I7 I6 I5 I4 I3 I2 I1 I0 DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
Figure 32. 2-Wire Serial Port Read Timing--Clock Stall High
Rev. 0 | Page 22 of 32
04806-0-007
04806-0-006
04806-0-005
SDI/O
04806-0-004
AD9956
INSTRUCTION BYTE
The instruction byte contains the following information:
Table 4.
D7 R/Wb D6 X D5 X D4 A4 D3 A3 D2 A2 D1 A1 D0 A0
MSB/LSB TRANSFERS
The AD9956 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the LSB first bit in Control Register 1 (CFR1<15>). The default value of this bit is low (MSB first). When CFR1 <15> is set high, the AD9956 serial port is in LSB first format. The instruction byte must be written in the format indicated by CFR1 <15>. If the AD9956 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. However, the instruction byte phase of the communications cycle still precedes the data transfer cycle. For MSB first operation, all data written to (read from) the AD9956 are in MSB first order. If the LSB mode is active, all data written to (read from) the AD9956 are in LSB first order.
TPRE CS TDSU SCLK TDHLD TSCLKW
R/Wb--Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. X, X--Bits 6 and 5 of the instruction byte are Don't Care. A4 to A0--Bits 4 to 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK--Serial Clock. The serial clock pin is used to synchronize data to and from the AD9956 and to run the internal state machines. The SCLK maximum frequency is 25 MHz. CS--Chip Select Bar. CS is an active low input that allows more than one device on the same serial communications line. The SDO and SDI/O pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select can be tied low in systems that maintain control of SCLK. SDI/O--Serial Data Input/Output. Data is always written to the AD9956 on this pin. However, this pin can be used as a bidirectional data line. CFR1<7> controls the configuration of this pin. The default value (0) configures the SDI/O pin as bidirectional. SDO--Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9956 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. I/O_RESET--A high signal on this pin resets the I/O port state machines without affecting the addressable registers' contents. An active high input on the I/O_RESET pin causes the current communication cycle to abort. After I/O_RESET returns low (0), another communication cycle can begin, starting with the instruction byte write. Note that when not in use, this pin should be forced low, because it floats to the threshold value.
SDI/O SYMBOL TPRE TSCLKW TDSU TDHLD
FIRST BIT MIN 6ns 40ns 6.5ns 0ns
SECOND BIT DEFINITION CS SETUP TIME PERIOD OF SERIAL DATA CLOCK (WRITE) SERIAL DATA SETUP TIME SERIAL DATA HOLD TIME
Figure 33. Timing Diagram for Data Write to AD9956
CS
TSCLKR
SCLK SDI/O SDO
FIRST BIT TDV
SECOND BIT
Figure 34. Timing Diagram for Data Read to AD9956
Rev. 0 | Page 23 of 32
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SYMBOL TDV TSCLKR
MAX DEFINITION 40ns DATA VALID TIME 400ns PERIOD OF SERIAL DATA CLOCK (READ)
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AD9956 REGISTER MAP AND DESCRIPTION
Table 5.
Register Name (Serial Address) Control Function Register 1 (CFR1) (0x00) Default Value/ Profile 0x00 0x00
Bit Range <31:24> <23:16>
(MSB) Bit 7 Open1 LOAD SRR @ I/O_UPDATE
Bit 6 Open1 Auto-Clr Frequency Accum. SDI/O Input Only PFD Input PowerDown Open1
Bit 5 Open1 AutoClr Phase Accum. Open1
Bit 4 Open1 Enable Sine Output Open1
Bit 3 Open1 Clear Frequency Accum. Open1
Bit 2 Open1 Clear Phase Accum. Open1
Bit 1 Open1 Linear Sweep Enable Open1
Bit 0 (LSB) PLL Lock Error Linear Sweep No Dwell Open1
<15:8>
LSB First
0x00
<7:0>
Digital PowerDown DAC PowerDown
PLLREF Crystal Enable Open1
SYNC_CLK Disable
Auto Sync Multiple AD9956s Open1
Software Manual Sync Open1
Hardware Manual Sync Internal Band Gap PowerDown PLL Lock Detect Enable Slew Rate Control
Control Function Register 2 (CFR2) (0x01)
<39:32>
Open1
<31:24>
Clock Driver Rising Edge <31:29>
Clock Driver Falling Edge Control <28:26> Clock Driver PowerDown Clock Driver Input Select <19:18>
<23:16>
RF Divider PowerDown
RF Divider Ratio <22:21>
High Speed Sync Enable Internal CML Driver DRV_RSET PLL Lock Detect Mode RF Div REFCLK Mux Bit
0x00
0x00
0x00
0x78
<15:8> <7:0> Rising Delta Frequency Tuning Word (RDFTW) (0x02) Falling Delta Frequency Tuning Word (FDFTW) (0x03) Rising Sweep Ramp Rate (RSRR) (0x04) Falling Sweep Ramp Rate (FSRR) (0x05) <23:16> <15:8> <7:0>
Open1
Divider M Control <15:12> Divider N Control <11:8> Open1 CP Current Scale <2:0> CP CP CP Polarity Full PD Quick PD Rising Delta Frequency Tuning Word <23:16> Rising Delta Frequency Tuning Word <15:8> Rising Delta Frequency Tuning Word <7:0>
0x00 0x07 0x00 0x00 0x00
<23:16> <15:8> <7:0>
Falling Delta Frequency Tuning Word <23:16> Falling Delta Frequency Tuning Word <15:8> Falling Delta Frequency Tuning Word <7:0>
0x00 0x00 0x00
<15:8> <7:0>
Rising Sweep Ramp Rate <15:8> Rising Sweep Ramp Rate <7:0>
0x00 0x00
<15:8> <7:0>
Rising Sweep Ramp Rate <15:8> Rising Sweep Ramp Rate <7:0>
0x00 0x00
1
In all cases, open bits must be written to 0. Rev. 0 | Page 24 of 32
AD9956
Register Name (Serial Address) Profile Control Register No. 0 (PCR0) (0x06) Bit 0 (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Open1 Phase Offset Word 0 (POW0) <13:8> Phase Offset Word 0 (POW0) <7:0> Frequency Tuning Word 0 (FTW0) <47:40> Frequency Tuning Word 0 (FTW0) <39:32> Frequency Tuning Word 0 (FTW0) <31:24> Frequency Tuning Word 0 (FTW0) <23:16> Frequency Tuning Word 0 (FTW0) <15:8> Frequency Tuning Word 0 (FTW0) <7:0> Open1 Phase Offset Word 1 (POW1) <13:8> Phase Offset Word 1 (POW1) <7:0> Frequency Tuning Word 1 (FTW1) <47:40> Frequency Tuning Word 1 (FTW1) <39:32> Frequency Tuning Word 1 (FTW1) <31:24> Frequency Tuning Word 1 (FTW1) <23:16> Frequency Tuning Word 1 (FTW1) <15:8> Frequency Tuning Word 1 (FTW1) <7:0> Open1 Phase Offset Word 2 (POW2) <13:8> Phase Offset Word 2 (POW2) <7:0> Frequency Tuning Word 2 (FTW1) <47:40> Frequency Tuning Word 2 (FTW2) <39:32> Frequency Tuning Word 2 (FTW2) <31:24> Frequency Tuning Word 2 (FTW2) <23:16> Frequency Tuning Word 2 (FTW2) <15:8> Frequency Tuning Word 2 (FTW2) <7:0> Open1 Phase Offset Word 3 (POW3) <13:8> Phase Offset Word 3 (POW3) <7:0> Frequency Tuning Word 3 (FTW3) <47:40> Frequency Tuning Word 3 (FTW3) <39:32> Frequency Tuning Word 3 (FTW3) <31:24> Frequency Tuning Word. 3 (FTW3) <23:16> Frequency Tuning Word 3 (FTW3) <15:8> Frequency Tuning Word 3 (FTW3) <7:0> Default Value/ Profile 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Profile Control Register No. 1 (PCR1) (0x07)
Profile Control Register No. 2 (PCR2) (0x08)
Profile Control Register No. 3 (PCR3) (0x09)
Bit Range <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0>
1
In all cases, open bits must be written to 0.
Rev. 0 | Page 25 of 32
AD9956
Default Value/ Profile 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Register Name (Serial Address) Profile Control Register No. 4 (PCR4) (0x0A)
Profile Control Register No. 5 (PCR5) (0x0B)
Profile Control Register No. 6 (PCR6) (0x0C)
Profile Control Register No. 7 (PCR7) (0x0D)
Bit Range <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0> <63:56> <55:48> <47:40> <39:32> <31:24> <23:16> <15:8> <7:0>
(MSB) Bit 7
Bit 6 Open1
Bit 5
Open1
Open1
Open1
Bit 4 Bit 3 Bit 2 Bit 1 Phase Offset Word 4 (POW4) <13:8> Phase Offset Word 4 (POW4) <7:0> Frequency Tuning Word 4 (FTW4) <47:40> Frequency Tuning Word 4 (FTW4) <39:32> Frequency Tuning Word 4 (FTW4) <31:24> Frequency Tuning Word 4 (FTW4) <23:16> Frequency Tuning Word 4 (FTW4) <15:8> Frequency Tuning Word 4 (FTW4) <7:0> Phase Offset Word 5 (POW5) <13:8> Phase Offset Word 5 (POW5) <7:0> Frequency Tuning Word 5 (FTW5) <47:40> Frequency Tuning Word 5 (FTW5) <39:32> Frequency Tuning Word 5 (FTW5) <31:24> Frequency Tuning Word 5 (FTW5) <23:16> Frequency Tuning Word 5 (FTW5) <15:8> Frequency Tuning Word 5 (FTW5) <7:0> Phase Offset Word 6 (POW6) <13:8> Phase Offset Word 6 (POW6) <7:0> Frequency Tuning Word 6 (FTW6) <47:40> Frequency Tuning Word 6 (FTW6) <39:32> Frequency Tuning Word 6 (FTW6) <31:24> Frequency Tuning Word 6 (FTW6) <23:16> Frequency Tuning Word 6 (FTW6) <15:8> Frequency Tuning Word 6 (FTW6) <7:0> Phase Offset Word 7 (POW7) <13:8> Phase Offset Word 7 (POW7) <7:0> Frequency Tuning Word 7 (FTW7) <47:40> Frequency Tuning Word 7 (FTW7) <39:32> Frequency Tuning Word 7 (FTW7) <31:24> Frequency Tuning Word 7 (FTW7) <23:16> Frequency Tuning Word 7 (FTW7) <15:8> Frequency Tuning Word 7 (FTW7) <7:0>
Bit 0 (LSB)
1
In all cases, open bits must be written to 0.
Rev. 0 | Page 26 of 32
AD9956
CONTROL FUNCTION REGISTER DESCRIPTIONS
Control Function Register 1 (CFR1)
This control register is comprised of four bytes, all of which must be written during a write operation involving CFR1. CFR1 is used to control various functions, features, and operating modes of the AD9956. The functionality of each bit(s) is described below. In general, the bit is named for the function it serves when the bit is set.
CFR1<31:25> Open. Unused locations. Write a Logic 0 CFR1<24> PLL Lock Error (Read-Only)
CFR1 <22> = 0 (default). Issuing an I/O_UPDATE has no effect on the current state of the frequency accumulator. CFR1 <22> = 1. Issuing an I/O_UPDATE signal to the part clears the current contents of the frequency accumulator for one sync-clock period.
CFR1 <21> Auto-Clear Phase Accumulator
When the device is operating in automatic synchronization mode or hardware manual synchronization mode (see below), the PLL_LOCK/ SYNC_IN pin behaves as the SYNC_IN. To determine whether or not the PLL has become unlocked while in synchronization mode, this bit serves as a flag to indicate that an unlocked condition has occurred within the phase frequency detector. Once set, the flag stays high until it is cleared by a readback of the value even though the loop might have relocked. Readback of the CFR1 register clears this bit. CFR1<24> = 0 indicates that the loop has maintained lock since the last readback. CFR1<24> = 1 indicates that the loop became unlocked at some point since the last readback of this bit.
CFR1<23> Load Sweep Ramp Rate at I/O_UPDATE, also known as Load SRR @ I/O_UPDATE
This bit enables the auto-clear function for the phase accumulator. The auto-clear function serves as a reset function for the phase accumulator, which then begins accumulating from a known phase value of 0. CFR1<21> = 0 (default). Issuing an I/O_UPDATE has no effect on the current state of the phase accumulator. CFR1<21> = 1. Issuing an I/O_UPDATE clears the current contents of the phase accumulator for one SYNC_CLK period.
CFR1 <20> Enable Sine Output
Two different trigonometric functions can be used to convert the phase angle to an amplitude value, cosine or sine. This bit selects the function used. CFR1<20> = 0 (default). The phase-to-amplitude conversion block uses a cosine function. CFR1<20> = 1. The phase-to-amplitude conversion block uses a sine function.
CFR1 <19> Clear Frequency Accumulator
The sweep ramp rate is set by entering a value to a down counter that is clocked by the SYNC_CLK. Each time a new step is taken in the linear sweep algorithm, the ramp rate value is passed from the linear sweep ramp rate register to this down counter. When set, CFR1<23>, enables the user to force the part to restart the countdown sequence for the current linear sweep step by toggling the I/O_UPDATE pin. CFR1<23> = 0 (default). The linear sweep ramp rate countdown value is loaded only upon completion of a countdown sequence. CFR1<23> = 1. The linear sweep ramp rate countdown value is reloaded, if an I/O_UPDATE signal is sent to the part during a sweep.
CFR1<22> Auto-Clear Frequency Accumulator
This bit serves as a static-clear or a clear-and-hold bit for the frequency accumulator. It prevents the frequency accumulator from incrementing the value as long as it is set. CFR1 <19> = 0 (default). The frequency accumulator operates normally. CFR1 <19> = 1. The frequency accumulator is cleared and held at a value of 0.
CFR1 <18> Clear Phase Accumulator
This bit serves as a static-clear or a clear-and-hold it for the phase accumulator. It prevents the phase accumulator from incrementing the value as long as it is set. CFR1 <18> = 0 (default). The phase accumulator operates normally. CFR1 <18> = 1. The phase accumulator is cleared and held at a value of 0.
This bit enables the auto-clear function for the frequency accumulator. The auto-clear function serves as a clear and release function for the frequency accumulator (which performs the linear sweep operation), which then begins sweeping from a known value of FTW0.
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AD9956
CFR1 <17> Linear Sweep Enable CFR1<7> Digital Power-Down
This bit turns on the frequency accumulator, which enables the DDS to perform linear sweeping. CFR1<17> = 0 (default). The DDS generates frequencies in single-tone mode. CFR1<17> = 1. The DDS uses the frequency accumulator to sweep the frequency tuning word being sent to the phase accumulator according to the values set in the delta frequency tuning word and delta frequency ramp rate registers. For a detailed explanation of this mode, see the linear sweep mode of operation section.
CFR1 <16> Linear Sweep No Dwell
This bit powers down the digital circuitry not directly related to the I/O port. The I/O port functionality is not suspended, regardless of the state of this bit. CFR1<7> = 0 (default). Digital logic operating as normal. CFR1<7> = 1. All digital logic not directly related to the I/O port is powered down. Internal digital clocks are suspended.
CFR1<6> Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency detector. It provides a way to gate external signals from the phase frequency detector itself. CFR1<6> = 0 (default). Phase frequency detector input buffers are functioning normally. CFR1<6> = 1. Phase frequency detector input buffers are powered down, isolating the phase frequency detector from the outside world.
CFR1<5> PLLREF Crystal Enable
This bit dictates the behavior of the DDS core upon completion of a linear sweep. CFR1<16> = 0 (default). Upon reaching the upper value of the sweep (FTW1), the DDS holds at the frequency value stored in FTW1. CFR1<16> = 1. Upon reaching the upper value of the sweep (FTW1), the DDS returns to the initial value in the sweep (FTW0) and continues to output that frequency until a new sweep is initiated (by bringing PS0 low and then high).
CFR1 <15> LSB First Serial Data Mode
The AD9956 phase frequency detector has an on-chip oscillator circuit. When enabled, the reference input to the phase frequency detector (PLLREF/PLLREF) can be driven by a crystal. CFR1<5> = 0 (default). Phase frequency detector reference input operates as a standard analog input. CFR1<5> = 1. Reference input oscillator circuit is enabled, allowing the use of a crystal for the reference of the phase frequency detector.
CFR1<4> SYNC_CLK Disable
The serial data transfer to the device can be either MSB first or LSB first. This bit controls that operation. CFR1<15> = 0 (default). Serial data transfer to the device is in MSB first mode. CFR1<15> = 1. Serial data transfer to the device is in LSB first mode.
CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9956 can act in 2-wire mode (SCLK and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit toggles the serial port between these two modes. CFR1<14> = 0 (default). Serial data transfer to the device is in 2-wire mode. The SDI/O pin is bidirectional. CFR1<14> = 1. Serial data transfer to the device is in 3-wire mode. The SDI/O pin is input only.
CFR1<13:8> Open
If synchronization of multiple devices is not required, the spectral energy resulting from this signal can be reduced by gating the output buffer off. This function gates the internal clock reference SYNC_CLK (SYSCLK/4) off of the SYNC_OUT pin. CFR1<4> = 0 (default). SYNC_CLK signal is present on the SYNC_OUT pin and is ready to be ported to other devices. CFR1<4> = 1. SYNC_CLK signal is gated off, putting the SYNC_OUT pin into a high impedance state.
CFR1<3> Automatic Synchronization
Unused locations. Write a Logic 0.
One of the synchronization modes of the AD9956 forces the DDS core to derive the internal reference from an external reference supplied on the SYNC_IN pin. For details on synchronization modes for the DDS core, see the Synchronization Modes for Multiple Devices section.
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AD9956
CFR1<3> = 0 (default). The automatic synchronization function of the DDS core is disabled. CFR1<3> = 1. The automatic synchronization function is on. The device is slaved to an external reference and adjusts the internal SYNC_CLK to match the external reference, which is supplied on the SYNC_IN input.
CFR1<2> Software Manual Synchronization CFR2<39> DAC Power-Down Bit
This bit powers down the DAC portion of the AD9956 and puts it into the lowest power dissipation state. CFR2<39> = 0 (default). DAC is powered on and operating. CFR2<39> = 1. DAC is powered down and the output is in a high impedance state.
CFR2<38> to CFR2<34> Open
Rather than relying on the part to automatically synchronize the internal clocks, the user can program the part to advance the internal SYNC_CLK one system clock cycle. This bit is self clearing and can be set multiple times. CFR1<2> = 0 (default). The SYNC_CLK stays in the current timing relationship to SYSCLK. CFR1<2> = 1. The SYNC_CLK advances the rising and falling edges by one SYSCLK cycle. This bit is then self-cleared.
CFR1<1> Hardware Manual Synchronization
Unused locations. Write a Logic 0.
CFR2<33> Internal Band Gap Power-Down
To shut off all internal quiescent current, the band gap needs to be powered down. This is normally not done because it takes a long time (~10 ms) for the band gap to power up and settle to its final value. CFR2<33> = 0. Even when all other sections are powered down, the band gap is powered up and is providing a regulated voltage. CFR2<33> = 1. The band gap is powered down.
CFR2<32> Internal CML Driver DRV_RSET
Similar to the software manual synchronization (CFR1<2>), this function enables the user to advance the SYNC_CLK rising edge by one system clock period. This bit enables the PLL_LOCK/SYNC_IN pin as a digital input. Once enabled, every rising edge on the SYNC_IN input advances the SYNC_CLK by one SYSCLK period. While enabled, the PLL_LOCK signal is not available on an external pin. However, loop out-of-lock events trigger a flag in the control register (CFR1<24>). CFR1<1> = 0 (default). The hardware manual synchronization function is disabled. Either the part is outputting the PLL_LOCK (CFR1<3> = 0), or it is using the SYNC_IN to slave the SYNC_CLK signal to an external reference provided on SYNC_IN (CFR1<3> = 1). CFR1<1> = 1. PLL_LOCK/SYNC_IN is set as a digital input. Each subsequent rising edge on this pin advances the SYNC_CLK rising edge by one SYSCLK period.
CFR1<0> High Speed Synchronization Enable Bit
To program the CML driver's output current, a resistor must be placed between the DRV_RSET pin and ground. This bit enables an internal resistor to program the output current of the driver. CFR2<32> = 0 (default). The DRV_RSET pin is enabled, and an external resistor must be attached to the CP_RSET pin to program the output current. CFR2<32> = 1. The CML current is programmed by the internal resistor and ignores the resistor on the DRV_REST pin.
CFR2<31:29> Clock Driver Rising Edge
This bit enables extra functionality in the auto synchronization algorithm, which enables the device to synchronize high speed clocks (SYNC_CLK > 62.5 MHz). CFR1<0> = 0 (default). High speed synchronization is disabled. CFR1<0> = 1. High speed synchronization is enabled.
These bits control the slew rate of the CML clock driver output's rising edge. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability; the contributions of each bit are cumulative. Table 6 describes how the bits increase the current. Note that the additional current is on only during the rising edge of the waveform for approximately 250 ps, but not on during the entire transition.
Table 6. CML Clock Driver Rising Edge Slew Rate Control Bits and Associated Surge Current
CFR2<31> = 1 CFR2<30> = 1 CFR2<29> = 1 7.6 mA 3.8 mA 1.9 mA
Control Function Register 2 (CFR2)
This control register is comprised of five bytes, which must be written during a write operation involving CFR2. With some minor exceptions, the CFR2 primarily controls analog and timing functions on the AD9956.
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AD9956
CFR2<28:26> Clock Driver Falling Edge Control
These bits control the slew rate of the CML clock driver output's falling edge. When these bits are on, additional current is sent to the output driver to increase the rising edge slew rate capability. Table 7 describes how the bits increase the current; the contributions of each bit are cumulative. Note that the additional current is on only during the rising edge of the waveform, for approximately 250 ps, but not on during the entire transition.
Table 7. CML Clock Drive Falling Edge Slew Rate Control Bits and Associated Surge Current
CFR2<28> = 1 CFR2<30> = 1 CFR2<29> = 1 5.4 mA 2.7 mA 1.35 mA
CFR2<22:21> = 00. RF Divider R = 1. Note that this is not the same as bypassing the RF divider.
CFR2<20> Clock Driver Power-Down
This bit powers down the CML clock driver circuit. CFR2<20> =1 (default). CML clock driver circuit is powered down. CFR2<20> = 0. CML clock driver is powered up.
CFR2<19:18> Clock Driver Input Select
These bits control the mux on the input for the CML clock driver. CFR2<19:18> = 00. The CML clock driver is disconnected from all inputs (and does not toggle). CFR2<19:18> = 01. The CML clock driver is driven by the PLLOSC input pin. CFR2<19:18> = 10 (default). The CML clock driver is driven by the output of the RF divider. CFR2<19:18> = 11. The CML clock driver is driven by the input of the RF divider
CFR2<17> Slew Rate Control Bit
CFR2<25> PLL_LOCK_DETECT Enable
This bit enables the PLL_LOCK/SYNC_IN pin as a lock detect output for the PLL. CFR2<25> = 0 (default).The PLL_LOCK_DETECT signal is disabled. CFR2<25> = 1. The PLL_LOCK_DETECT signal is enabled.
CFR2<24> PLL_LOCK_DETECT Mode
This bit toggles the modes of the PLL_LOCK_DETECT function. The lock detect can either be a status indicator (locked or unlocked), or it can indicate a lead-lag relationship between the two phase frequency detector inputs. CFR2<24> = 0 (default). The lock detect acts as a status indicator (PLL is locked 0 or unlocked 1). CFR2<24> = 1. The lock detect acts as a lead/lag indicator. A 1 on the PLL_LOCK pin means that the PLLOSC pin lags the reference. A 0 means that the PLLOSC pin leads the reference.
CFR2<23> RF Divider Power-Down
Even without the additional surge current supplied by the rising edge slew rate control bits and the falling edge slew rate control bits, the device applies a default 7.6 mA surge current to the rising edge and a 4.05 mA surge current to the falling edge. This bit disables all slew rate enhancement surge current, including the default values. CFR2<17> = 0 (default). The CML driver applies default surge current to rising and falling edges. CFR2<17> = 1. Driver applies no surge current during transitions. The only current is the continuous current.
CFR2<16> RF Divider SYSCLK Mux Bit
This bit powers the RF divider down to save power when not in used. CFR2<23> = 0 (default). RF divider is on. CFR2<23> = 1. RF divider is powered down and an alternate path between the REFCLK inputs and SYSCLK is enabled.
CFR2<22:21> RF Divider Ratio
This bit toggles the mux to control whether the RF divider output or input is supplying SYSCLK to the device. CFR2<16> = 0 (default). The RF divider output supplies the DDS SYSCLK. CFR2<16> = 1. The RF divider input supplies the DDS SYSCLK (bypass the divider). Note that regardless of the condition of the configuration of the clock input, the DDS SYSCLK must not exceed the maximum rated clock speed.
These two bits control the RF divider ratio (/R). CFR2<22:21> = 11 (default). RF Divider R = 8. CFR2<22:21> = 10. RF Divider R= 4. CFR2<22:21> = 01. RF Divider R = 2.
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AD9956
CFR2<15:12> PLLREF Divider Control Bits (/M)
These 4 bits set the PLLREF divider (/M) ratio where M is a value equal to 1 to 16. CFR2<15:12> = 0000 means that M = 1 and CFR2<15:12> = 1111 means that M = 16, or simply, M = CFR2<15:12> + 1.
CFR2<15:12> = 0000 0001 0010 0011 0100 0101 0110 0111 M= 1 2 3 4 5 6 7 8 CFR2<15:12> = 1000 1001 1010 1011 1100 1101 1110 1111 M= 9 10 11 12 13 14 15 16
CFR2<5> = 1. The charge pump is configured to operate with a ground referenced VCO. If PLLOSC lags PLLREF, the charge pump will attempt to drive the VCO control node voltage lower. If PLLOSC leads PLLREF, the charge pump will attempt to drive the VCO control node voltage higher.
CFR2<4> Charge Pump Full Power-Down
This bit, when set, will put the charge pump into a full powerdown mode. CFR2<4> = 0 (default). The charge pump is powered on and operating normally. CFR2<4> = 1. The charge pump is completely powered down.
CFR2<3> Charge Pump Quick Power-Down
CFR2<11:8> PLLREF Divider Control Bits (/N)
These 4 bits set the PLLOSC divider (/N) ratio where N is a value equal to 1 to 16. CFR2<11:8> = 0000 means that N = 1 and CFR2<11:8> = 1111 means that N = 16, or N = CFR2<11:8> + 1.
CFR2<15:12> = 0000 0001 0010 0011 0100 0101 0110 0111 N= 1 2 3 4 5 6 7 8 CFR2<11:8> = 1000 1001 1010 1011 1100 1101 1110 1111 N= 9 10 11 12 13 14 15 16
Rather than power down the charge pump, which can take a long time to recover from, a quick power-down mode, which powers down only the charge pump output buffer, is included. While this doesn't reduce the power consumption significantly, it does shut off the output to the charge pump and allows it to come back on in a rapidly. CFR2<3> = 0 (default). The charge pump is powered on and operating normally. CFR2<3> = 1. The charge pump is on and running, but the output buffer is powered down.
CFR2<2:0> Charge Pump Current Scale.
CFR2<7:6> Open
Unused locations. Write a Logic 0.
CFR2<5> CP Polarity
A base output current from the charge pump is determined by a resistor connected from the CP_RSET pin to ground (see the PLL Circuitry section). However, it is possible to multiply the charge pump output current by a value from 1:8 by programming these bits. The charge pump output current are scaled by CFR2<2:0> +1. CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8).
CFR2<2:0> 000 001 010 011 100 101 110 111 Scale Factor 1 2 3 4 5 6 7 8
This bit sets the polarity of the charge pump, in response to a ground referenced or a supply referenced VCO. CFR2<5> = 0 (default). The charge pump is configured to operate with a supply referenced VCO. If PLLOSC lags PLLREF, the charge pump will attempt to drive the VCO control node voltage higher. If PLLOSC leads PLLREF, the charge pump will attempt to drive the VCO control node voltage lower.
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AD9956 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 35. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm x 7 mm Body (CP-48) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9956YCPZ1 AD9956YCPZ-REEL1 AD9956/PCB Temperature Range -40C to +125C -40C to +125C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP) 48-Lead Lead Frame Chip Scale Package (LFCSP), Tape and Reel Evaluation Board Package Option CP-48 CP-48
1
Z = Pb-free part.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04806-0-7/04(0)
Rev. 0 | Page 32 of 32

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